Reduction of parameters in fully connected layers of neural networks

ABSTRACT

The present disclosure is drawn to the reduction of parameters in fully connected layers of neural networks. For a layer whose output is defined by y=Wx, where y is the output vector, x is the input vector, and W is a matrix of connection parameters, vectors u ij  and    ij  are defined and submatrices W i,j  are computed as the outer product of u ij  and    ij , so that W i,j =   ij   u ij , and W is obtained by appending submatrices W i,j .

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application claims priority under 35 U.S.C. 119(e) of U.S. Provisional Patent Application No. 62/337,566 filed on May 17, 2016, the contents of which are hereby incorporated by reference.

TECHNICAL FIELD

The present disclosure relates to creating layers for neural networks and particularly, to creating fully connected layers.

BACKGROUND OF THE ART

Artificial neural networks are mathematical models inspired by biological neural networks. They are used to approximate functions that can depend on a large number of unknown inputs. Neural networks are generally presented as systems of interconnected “neurons” which exchange messages between each other. The connections may have numeric weights that can be tuned using various optimization methods, for example stochastic gradient descent.

A deep neural network is made up of many layers. A layer, for example, may have n inputs (x₁, x₂, . . . , x_(n)) and m outputs (y₁, y₂, . . . , y_(m)). The number of inputs may be different from the number of outputs, and may also be different for different layers. Each layer maps the inputs to the outputs, in a way that is specific to the type of layer. The outputs from one layer may be the inputs to the next layer.

One type of layer found in neural networks is a fully connected layer. It connects every input to every output, such that y_(i)=w_(i,1)*x₁+w_(i,2)*x₂+ . . . +w_(i,n)*x_(n). This may also be represented using matrices as y=W.x, where W is an m x n matrix. When implementing the neural network on a computer, n x m parameters are loaded from memory and n x m computations are performed. Some of the larger layers of neural networks have up to n=9216 and m=4096. With 32-bit weights, this requires 150 MB for each iteration. Memory bandwidth is expensive in embedded device implementations.

Therefore, there is a need for improvement.

SUMMARY

The present disclosure is drawn to the reduction of parameters in fully connected layers of neural networks. For a layer whose output is defined by y=Wx, where y is the output vector, x is the input vector, and W is a matrix of connection parameters, vectors u_(ij) and

_(ij) are defined and submatrices W_(i,j) are computed as the outer product of u_(ij) and

_(ij), so that W_(i,j)=

_(ij)

u_(ij), and W is obtained by appending submatrices W_(i,j).

In accordance with a broad aspect, there is provided a method for creating a neural network layer. An n-dimensional input vector x and an m-dimensional output vector y are defined. The output vector y is partitioned into equally sized subvectors y_(i) of length s and partitioning the input vector x into equally sized subvectors x_(j) of length t. A vector u_(ij) of length t and a vector

_(ij) of length s are defined for i=(1, . . . , m/s) and j=(1, . . . , n/t). Submatrices W_(ij) are computed as an outer product of the vector u_(ij) and the vector

_(ij) so that W_(ij)=u_(ij) ^(T)

_(ij), and the output vector y is determined from y=W·x, where W is a matrix composed of all submatrices W_(ij) for i=(1, . . . , m/s) and j=(1, . . . n/t).

In some embodiments, determining the output vector y from y=W·x comprises computing y_(i)=Σ_(j=1) ^(n/t)(W_(ij)x_(j)) and determining the output vector y as y=[y₁, y₂, y₃, ym_(/s)].

In some embodiments, determining the output vector y from y=W·x comprises appending submatrices W_(ij) to obtain matrix Wand computing y=W·x.

In some embodiments, the method further comprises storing the vectors

_(ij) and u_(ij). In some embodiments, the method further comprises retrieving the vectors

_(ij) and u_(ij) to compute the matrices W_(i,h).

In some embodiments, the neural network is a feedforward neural network and/or a deep neural network.

In some embodiments, the method further comprises learning the vectors u_(ij) and

_(ij) during a training phase of the neural network.

In accordance with another broad aspect, there is provided a system for creating a neural network layer. The system comprises a processing unit and a non-transitory memory communicatively coupled to the processing unit and comprising computer-readable program instructions. The instructions are executable by the processing unit for defining an n-dimensional input vector x and an m-dimensional output vector y. The output vector y is partitioned into equally sized subvectors y_(i) of length s and partitioning the input vector x into equally sized subvectors x_(j) of length t. A vector u_(ij) of length t and a vector

_(ij) of length s are defined for i=(1, . . . , m/s) and j=(1, . . . , n/t). Submatrices W_(ij) are computed as an outer product of the vector u_(ij) and the vector

_(ij) so that W_(ij)=u_(ij) ^(T)

_(ij), and the output vector y is determined from y=W·x, where W is a matrix composed of all submatrices W_(ij) for i=(1, . . . , m/s) and j=(1, . . . , n/t).

In accordance with yet another broad aspect, there is provided a method for implementing a neural network layer. The method comprises receiving an n-dimensional input vector x and retrieving from memory vector

_(ij) of length s and vector u_(ij) of length t. The input vector x is partitioned into equally sized subvectors x_(j) of length t and submatrices W_(ij) are computed as an outer product of the vector u_(ij) and the vector

_(ij) so that W_(ij)=u_(ij) ^(T)

_(ij). The output vector y is determined from y=W·x, where W is a matrix composed of all submatrices W_(ij) for i=(1, . . . , m/s) and j=(1, . . . , n/t).

In some embodiments, determining the output vector y from y=W·x comprises computing y_(i)=Σ_(j=1) ^(n/t)(W_(ij)x_(j)) and determining the output vector y as y=[y₁, y₂, y₃, . . . , y_(/s)].

In some embodiments, determining the output vector y from y=W·x comprises appending submatrices W_(ij) to obtain matrix W and computing y=W·x.

In some embodiments, the neural network is a feedforward neural network and/or a deep neural network.

In accordance with another broad aspect, there is provided a system for implementing a neural network layer. The system comprises a processing unit and a non-transitory memory communicatively coupled to the processing unit and comprising computer-readable program instructions. The instructions are executable by the processing unit for receiving an n-dimensional input vector x and retrieving from memory vector

_(ij) of length s and vector u_(ij) of length t. The instructions are also executable for partitioning the input vector x into equally sized subvectors x_(j) of length t and computing submatrices W_(ij) as an outer product of the vector u_(ij) and the vector

_(ij) so that W_(ij)=u_(ij) ^(T)

_(ij). The output vector y is determined from y=W·x, where W is a matrix composed of all submatrices W_(ij) for i=(1, . . . , m/s) and j=(1, . . . , n/t).

In some embodiments, determining the output vector y from y=W·x comprises computing y_(i)=Σ_(j=1) ^(n/t)(W_(ij)x_(j)) and determining the output vector y as y=[y₁, y₂, y₃, . . . , ym_(/s)].

In some embodiments, determining the output vector y from y=W·x comprises appending submatrices W_(ij) to obtain matrix W and computing y=W·x.

In some embodiments, the neural network is a feedforward neural network and/or a deep neural network.

BRIEF DESCRIPTION OF THE DRAWINGS

Further features and advantages of the present invention will become apparent from the following detailed description, taken in combination with the appended drawings, in which:

FIG. 1 is a graphical illustration of a fully connected layer of a neural network, as per the prior art;

FIG. 2 is a graphical illustration of a local connection pattern between x_(j) and y_(i), in accordance with one embodiment;

FIGS. 3A and 3B are graphical illustrations of a tiled outer product layer in accordance with two embodiments;

FIG. 4A is a flowchart of a method for creating a fully-connected layer for use in a neural network in accordance with a first embodiment;

FIG. 4B is a flowchart of a method for creating a fully-connected layer for use in a neural network in accordance with a second embodiment;

FIG. 5 is a block diagram of an example system for implementing the method of FIGS. 4A and 4B; and

FIG. 6 is a comparative graph of the accuracy of a network having a fully connected layer compared to the same network having the fully connected layer replaced by a tiled outer product layer.

It will be noted that throughout the appended drawings, like features are identified by like reference numerals.

DETAILED DESCRIPTION

Referring to FIG. 1, there is illustrated a fully connected layer 100 of a neural network (not shown), as per the prior art. In this example, n inputs 102 ₁, 102 ₂, 102 ₃ . . . 102 _(n) are connected to m outputs 104 ₁, 104 ₂, . . . 104 _(m). More specifically, each input 102 ₁, 102 ₂, 102 ₃ . . . 102 _(n) is connected to each output 104 ₁, 104 ₂, . . . 104 _(m) via a direct connection 106 _(1,1), 106 _(2,1), . . . 106 _(m,n). Each connection 106 _(1,1), 106 _(2,1), . . . 106 _(m,n) corresponds to a parameter used to attenuate or amplify a signal going from the inputs 102 ₁, 102 ₂, 102 ₃ . . . 102 _(n) to the outputs 104 ₁, 104 ₂, . . . 104 _(m) and/or to reverse a sign of the signal.

The n inputs 102 ₁, 102 ₂, 102 ₃ . . . 102 _(n) are represented mathematically as an n-dimensional input vector x. The m outputs 104 ₁, 104 ₂, . . . 104, are represented mathematically as an m-dimensional output vector. The connections 106 _(1,1), 106 _(2,1), . . . 106 _(m,n) correspond to a matrix W such that the output vector y is given by:

y=W·x   (1)

The input vector x may be partitioned into equally sized subvectors x_(j) of length t where t is a divisor of n. Similarly, the output vector y may be partitioned into equally sized subvectors y_(i) of length s where s is a divisor of m:

y=[y₁, y₂, y₃, . . . ym_(/s)]  (2)

x=[x₁, x, x₃, . . . , xn_(/t)]  (3)

Vectors x and y may thus be obtained by concatenation of all x_(j) and all y_(i) subvectors, respectively. The matrix W is partitioned into equally sized s x t dimensional submatrices W_(i,j):

$W = \begin{bmatrix} W_{1,1} & W_{1,2} & \ldots & W_{1,j} & \ldots & W_{1,\frac{n}{t}} \\ W_{2,1} & W_{2,2} & \ldots & W_{2,j} & \ldots & W_{2,\frac{n}{t}} \\ \ldots & \ldots & \ldots & \ldots & \ldots & \ldots \\ W_{i,1} & W_{i,2} & \ldots & W_{i,j} & \ldots & W_{i,\frac{n}{t}} \\ \ldots & \ldots & \ldots & \ldots & \ldots & \ldots \\ W_{\frac{m}{s},1} & W_{\frac{m}{s},2} & \ldots & W_{\frac{m}{s},j} & \ldots & W_{\frac{m}{s},\frac{n}{t}} \end{bmatrix}$

Each submatrix W_(i,j) connects the jth group of input nodes to the ith group of output nodes. The ith subvector y_(i) of the output vector y may then be represented as:

y _(i)=Σ_(j=1) ^(n/t) W _(i,j) ·x _(j)   (4)

Performing this computation for all i ∈ {1, 2, . . . , m/s}, the entire output vector y is computed. In order to reduce the number of parameters needed for the computation of the output vector, each submatrix W_(i,j) is represented as an outer product of two vectors. The first vector is vector

_(ij) of length s and the second vector is vector u_(ij) of length t, for all i c {1, 2, . . . , n/t} and j ∈ {1, 2, . . . , m/s},so that:

W_(i,j)≈

_(ij)

u_(ij)   (5)

Replacing equation (5) into equation (4), the i^(th) subvector y_(i) of the output vector y becomes:

y _(i)≈Σ_(j=1) ^(n/t)(

_(ij)

u _(ij))·x _(j)   (6)

Equation (6) can be equivalently written as:

y _(i)≈Σ_(j=1) ^(n/t)

_(ij)(u _(ij) ^(T) x _(j)) tm (7)

where u_(ij) is a column vector and u_(ij) ^(T) is a row vector.

In equation (7), the dot product u_(ij) ^(T)x_(j) yields a scalar which is then multiplied by the vector

_(ij). The connection between the input nodes x_(j) and output nodes y_(i) is graphically represented in FIG. 2 for s=2 and t=4. Input nodes 102 ₁, 102 ₂, 102 ₃, 102 ₄ are connected to output nodes 104 ₁, 104 ₂ via first vectors 108 ₁, 108 ₂, 108 ₃, 108 ₄ and second vectors 110 ₁, 110 ₂. The scalar product of u_(ij) ^(T)x_(j) is illustrated as intermediary node 112 ₁.

The architecture illustrated in FIG. 2 is a local connection pattern between x_(j) and y_(i). It may be referred to as a tiled outer product layer for s=m and n=t, and is equivalent to a fully connected layer when s=t=1. Generally, a tiled outer product layer may have many instances of the architecture of FIG. 2 embedded in it. Using the tiled outer product layer, the number of parameters per submatrix is reduced from (s×t) to (s+t). For example, suppose the following vectors:

u_(ij) ^(T)=[u₁, u₂, u₃, u₄]

_(ij)=[

₁,

₂]

where u_(ij) ^(T) is a row vector and

_(ij) is a column vector. The outer product, as represented by equation (5) is a 2×4 matrix as per Table 1:

TABLE 1 u₁ u₂ u₃ u₄ v₁ u₁v₁ u₂v₁ u₃v₁ u₄v₁ v₂ u₁v₂ u₂v₂ u₃v₂ u₄v₂

Only (2+4=6) parameters, namely u₁, u₂, u₃, u₄ and

₁,

₂ are needed to represent the (2×4=8) entries of W_(i,j). Therefore, the overall number of parameters needed is reduced by a factor of :

$\frac{s \times t}{s + t}$

An example graph 300 is illustrated in FIG. 3A for n=8, m=6, s=4, t=2. In FIG. 3A, the input nodes are grouped to form two subsets x₁ and x₂. Subset x₁ comprises nodes 302 a-d, and subset x₂ comprises nodes 304 a-d. The middle layer is formed by nodes 112 ₁ through 112 ₆ in groupings of two nodes. Each node in x₁ is connected to a node in each of the middle groupings. As illustrated each node in x₁ is connected to nodes 112 ₁, 112 ₃ and 112 ₅. Similarly, each node in x₂ is connected to nodes 112 ₂, 112 ₄ and 112 ₆. Nodes 112 ₁ and 112 ₂ are each connected to nodes 306 a and 306 b, which form group y₁. Similarly, nodes 112 ₃ and 112 ₄ are connected to nodes 308 a and 308 b which form group y₂, while nodes 112 ₅ and 112 ₆ are connected to nodes 310 a and 310 b which form group y₃.

Another example graph 350 is illustrated in FIG. 3B for n=12, m=6, s=4, t=2. In graph 350, the input nodes are grouped to form three subsets x₁, x₂, x₃. Subset x₁ comprises nodes 352 a-352 d, subset x₂ comprises nodes 354 a-354 d, and subset x₃ comprises nodes 356 a-356 d. The middle layer is formed by nodes 122 ₁ through 122 ₉ in groupings of three nodes. Each node in x₁ is connected to a node in each of the middle groupings. More specifically, each node in x₁ is connected to nodes 122 ₁, 122 ₄,122 ₇. Similarly, each node in x₂ is connected to nodes 122 ₂, 122 ₅,122 ₈, and each node in x₃ is connected to nodes 122 ₃, 122 ₆,122 ₉. Nodes 122 ₁, 122 ₂, 122 ₃ are each connected to nodes 356 a and 356 b which form group y_(l). Similarly, nodes 122 ₄, 122 ₅, 122 ₆ are each connected to nodes 360 a and 360 b which form group y₂, while nodes 122 ₇, 122 ₈, 122 ₉ are each connected to nodes 362 a and 362 b which form group y₃.

In both graphs 300 and 350, there are a total of (s+t) parameters needed to represent (s×t) entries of W_(i,j). It should be understood that the intermediate nodes 112 ₁, . . . , 112 _(nxm) are not actual nodes in the neural network. They are merely a graphical representation of the intermediate step performed to compute y_(i) when the submatrix W_(i,j) is represented by the outer product of two vectors

_(ij) and u_(ij), as per equations (5), (6), and (7).

Referring now to FIG. 4A, there is illustrated a method 400 for creating a layer for use in a neural network, such as but not limited to a feedforward neural network. In some embodiments, the neural network is a deep neural network. At step 402, an n-dimensional input vector and an m-dimensional output vector are defined. The input and output vectors may be of any size. In some embodiments, the input and output vectors are equal to or less than 8192 and 2048, respectively. Other embodiments may also apply.

At step 404, divisors s and t of m and n, respectively, are selected. Through this step, the tile size for the tiled product layer is set, as used in tiled (or blocked) matrix-vector or matrix-matrix multiplication, where s corresponds to the height of the tile and t corresponds to the width of the tile. In some embodiments, the divisors s and t are equal to or less than 64 and 64, respectively.

At step 406, the input vector and the output vector are each partitioned using the divisors s and t. Specifically, the output vector y is partitioned into equally sized subvectors y_(i) of length s, where y=[y₁, y₂, y₃, . . . , ym_(/s)] and the input vector x is partitioned into equally sized subvectors x_(i) of length t, where x=[x₁, x, x₃, . . . , xn_(/t)].

At step 408, a vector u_(ij) of length t and a vector

_(ij) of length s are defined for i=(1, . . . , m/s) and j=(1, . . . , n/t). At step 410, the outer product of u_(ij) and

_(ij) is computed to produce submatrices W_(ij), so that W_(ij)=u_(ij) ^(T)

_(ij). Once the submatrices W_(ij) are computed from the outer product of u_(ij) and

_(ij), the output vector y is determined from y=W·x, where W is a matrix composed of all submatrices W_(ij) for i=(1, . . . , m/s) and j=(1, . . . , n/t), as per step 411.

An embodiment of step 411 is illustrated at steps 412 and 414. At step 412, output subvector y_(i) is computed as the product of W_(ij) and x_(j), so that y_(i)=Σ_(j=1) ^(n/t)

_(ij)(u_(ij) ^(T)x_(j)). At step 414, all y_(i) values are concatenated to obtain the output vector y.

An alternative embodiment of step 411 is illustrated in FIG. 4B at steps 416 and 418. At step 416, submatrices W_(ij) are appended to obtain matrix W, such that:

$W = \begin{bmatrix} W_{1,1} & W_{1,2} & \ldots & W_{1,j} & \ldots & W_{1,\frac{n}{t}} \\ W_{2,1} & W_{1,2} & \ldots & W_{2,j} & \ldots & W_{2,\frac{n}{t}} \\ \ldots & \ldots & \ldots & \ldots & \ldots & \ldots \\ W_{i,1} & W_{i,2} & \ldots & W_{i,j} & \ldots & W_{i,\frac{n}{t}} \\ \ldots & \ldots & \ldots & \ldots & \ldots & \ldots \\ W_{\frac{m}{s},1} & W_{\frac{m}{s},2} & \ldots & W_{\frac{m}{s},j} & \ldots & W_{\frac{m}{s},\frac{n}{t}} \end{bmatrix}$

At step 418, the output vector y is obtained as the product of matrix W and input vector x: y=Wx.

In some embodiments, the method 400 comprises a step of storing vectors

_(ij) and u_(ij). Therefore, instead of storing each submatrix W_(ij), the vectors

_(ij) and u_(ij) are stored, and W_(ij) is computed during feed-forward using the outer products when

_(ij) and u_(ij) are retrieved. During training, the parameters

_(ij) and u_(ij) are learned.

Referring to FIG. 5, the methods of FIGS. 4A and 4B may be implemented on one or more computing device 500. Computing device 500 may comprise one or more processors 504 and one or more computer-readable memories 502 storing machine-readable instructions 506 executable by processor 504 and configured to cause processor 504 to generate one or more outputs 510 based on one or more inputs 508. The inputs may comprise values for any one of m, n, s, and t. The inputs 508 may also comprise the input and/or output vectors x and y, respectively. The outputs 510 may comprise the vectors

_(ij) and u_(ij), the outer product of vectors

_(ij) and u_(ij), and/or the output subvectors y_(i) as defined by equations (6) or (7). In some embodiments, the outputs 510 comprise the submatrices W_(ij) after having been computed from the outer product of

_(ij) and u_(ij). Other inputs 508 and outputs 510 may also apply.

Processor 504 may comprise any suitable device(s) configured to cause a series of steps to be performed by computer 500 so as to implement a computer-implemented process such that instructions 506, when executed by computer 500 or other programmable apparatus, may cause the functions/acts specified in the methods described herein to be executed. Processor 504 may comprise, for example, any type of general-purpose microprocessor or microcontroller, a digital signal processing (DSP) processor, an integrated circuit, a field programmable gate array (FPGA), a reconfigurable processor, other suitably programmed or programmable logic circuits, or any combination thereof.

Memory 502 may comprise any suitable known or other machine-readable storage medium. Memory 502 may comprise non-transitory computer readable storage medium such as, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. Memory 502 may include a suitable combination of any type of computer memory that is located either internally or externally to computer 500 such as, for example, random-access memory (RAM), read-only memory (ROM), compact disc read-only memory (CDROM), electro-optical memory, magneto-optical memory, erasable programmable read-only memory (EPROM), and electrically-erasable programmable read-only memory (EEPROM), Ferroelectric RAM (FRAM) or the like. Memory 502 may comprise any storage means (e.g. devices) suitable for retrievably storing machine-readable instructions 506 executable by processor 504.

Various aspects of the present disclosure may be embodied as systems, devices, methods and/or computer program products. Accordingly, aspects of the present disclosure may take the form of an entirely hardware embodiment, an entirely software embodiment (including firmware, resident software, micro-code, etc.) or an embodiment combining software and hardware aspects. Furthermore, aspects of the present disclosure may take the form of a computer program product embodied in one or more non-transitory computer readable medium(ia) (e.g., memory 502) having computer readable program code (e.g., instructions 506) embodied thereon. The computer program product may, for example, be executed by computer 500 to cause the execution of one or more methods disclosed herein in entirety or in part.

Computer program code for carrying out operations for aspects of the present disclosure in accordance with instructions 506 may be written in any combination of one or more programming languages, including an object oriented programming language such as Java, Smalltalk, C++ or the like and conventional procedural programming languages, such as the “C” programming language or other programming languages. Such program code may be executed entirely or in part by computer 500 or other processing device(s). It is understood that, based on the present disclosure, one skilled in the relevant arts could readily write computer program code for implementing the methods disclosed herein.

In some embodiments, computer 500 may be used to perform a method for implementing a neural network having at least one layer. An n-dimensional input vector x is received as input 508. The method comprises retrieving from memory first vectors

_(ij) ∈

^(s) and second vectors u_(ij) ∈

^(t), where s is a divisor of m and t is a divisor of n for partitioning an output vector y into equally sized subvectors y_(i) ∈

^(s) and partitioning the input vector x into equally sized subvectors x_(j) ∈

^(t). The instructions 506 are configured to compute the outer products of the first vectors

_(ij) and the second vectors u_(ij) to obtain the submatrices W_(i,j) ∈

^(s x t), and to compute output subvectors y_(i) as y_(i)=Σ_(j=1) ^(n/t)W_(i,j)·x_(j). Alternatively, the instructions 506 are configured to compute the output subvectors y_(i) as y_(i)=Σ_(j=1) ^(n/t)

_(ij)

u_(ij))·x_(j). The output subvectors y_(i) may be provided as part of outputs 510.

Computer-executable instructions 506 may be in many forms, including program modules, executed by one or more computers or other devices. Generally, program modules include routines, programs, objects, components, data structures, etc., that perform particular tasks or implement particular abstract data types. Typically the functionality of the program modules may be combined or distributed as desired in various embodiments.

Referring to FIG. 6, there is illustrated a graph comparing the accuracy obtained with a neural network containing a fully connected layer 602 to the accuracy obtained with the same network with the fully connected layer replaced with a tiled outer product layer 604, 606, according to an embodiment similar to that described above, using the same data set with different parameters. The neural network 604 contains tiled outer product layer with n=8192, m=2048, s=64, t=32. The neural network 606 contains tiled outer product layer with n=8192, m=2048, s=64, t=64. As shown, the accuracy is substantially similar, and the networks with tiled outer product layers 604, 606 use less parameters, thus leading to a savings in memory space. The savings are proportional to (s*t)/(s+t).

Various aspects of the present disclosure may be used alone, in combination, or in a variety of arrangements not specifically discussed in the embodiments described in the foregoing and is therefore not limited in its application to the details and arrangement of components set forth in the foregoing description or illustrated in the drawings. For example, aspects described in one embodiment may be combined in any manner with aspects described in other embodiments. Although particular embodiments have been shown and described, it will be obvious to those skilled in the art that changes and modifications may be made without departing from this invention in its broader aspects. The appended claims are to encompass within their scope all such changes and modifications. 

1. A method for creating a neural network layer, the method comprising: defining an n-dimensional input vector x and an m-dimensional output vector y; selecting a divisor s of m and a divisor t of n; partitioning the output vector y into equally sized subvectors y_(l) of length s and partitioning the input vector x into equally sized subvectors x_(j) of length t; defining a vector u_(ij) of length t and a vector

_(ij) of length s for i=(1, . . . , m/s) and j=(1, . . . , n/t); computing submatrices W_(ij) as an outer product of the vector u_(ij) and the vector

_(ij) so that W_(ij)=u_(ij) ^(T)

_(ij), and determining the output vector y from y=W·x, where W is a matrix composed of all submatrices W_(ij) for i=(1, . . . , m/s) and j=(1, . . . , n/t).
 2. The method of claim 1, wherein determining the output vector y from y=W·x comprises: computing y_(i)=Σ_(j=1) ^(n/t)(W_(ij)x_(j)); and determining the output vector y as y=[y₁, y₂, y₃, . . . , ym_(/s)].
 3. The method of claim 1, wherein determining the output vector y from y=W·x comprises: appending submatrices W_(ij) to obtain matrix W; and computing y=W·x.
 4. The method of claim 1, further comprising storing the vectors

_(ij) and u_(ij).
 5. The method of claim 4, further comprising retrieving the vectors

_(ij) and u_(ij) to compute the matrices W_(i,j).
 6. The method of claim 1, wherein the neural network is a feedforward neural network.
 7. The method of claim 1, wherein the neural network is a deep neural network.
 8. The method of claim 1, further comprising learning the vectors u_(ij) and

_(ij) during a training phase of the neural network.
 9. A system for creating a neural network layer, the system comprising: a processing unit; and a non-transitory memory communicatively coupled to the processing unit and comprising computer-readable program instructions executable by the processing unit for: defining an n-dimensional input vector x and an m-dimensional output vector y; selecting a divisor s of m and a divisor t of n; partitioning the output vector y into equally sized subvectors y_(i) of length s and partitioning the input vector x into equally sized subvectors x_(j) of length t; defining a vector u_(ij) of length t and a vector

_(ij) of length s for i=(1, . . . , m/s) and j=(1, . . . , n/t); computing submatrices W_(ij) as an outer product of the vector u_(ij) and the vector

_(ij) so that W_(ij)=u_(ij) ^(T)

_(ij); and determining the output vector y from y=W·x, where W is a matrix composed of all submatrices W_(ij) for i=(1, . . . , m/s) and j=(1, . . . , n/t).
 10. A method for implementing a neural network layer, the method comprising: receiving an n-dimensional input vector x; retrieving from memory vector

_(ij) of length s and vector u_(ij) of length t; partitioning the input vector x into equally sized subvectors x_(j) of length t; computing submatrices W_(ij) as an outer product of the vector u_(ij) and the vector

_(ij) so that W_(ij)=u_(ij) ^(T)

_(ij); and determining the output vector y from y=W·x, where W is a matrix composed of all submatrices W_(ij) for i=(1, . . . , m/s) and j=(1, . . . , n/t).
 11. The method of claim 10, wherein determining the output vector y from y=W·x comprises: computing y_(i)=Σ_(j=1) ^(n/t)(W_(ij)x_(j)); and determining the output vector y as y=[y₁, y₂, y₃, . . . , ym_(/s)].
 12. The method of claim 10, wherein determining the output vector y from y=W·x comprises: appending submatrices W_(ij) to obtain matrix W; and computing y=W·x.
 13. The method of claim 10, wherein the neural network is a feedforward neural network.
 14. The method of claim 10, wherein the neural network is a deep neural network.
 15. A system for implementing a neural network layer, the system comprising: a processing unit; and a non-transitory memory communicatively coupled to the processing unit and comprising computer-readable program instructions executable by the processing unit for: receiving an n-dimensional input vector x; retrieving from memory vector

_(ij) of length s and vector u_(ij) of length t; partitioning the input vector x into equally sized subvectors x_(j) using divisor t; computing submatrices W_(ij) as an outer product of the vector u_(ij) and the vector

_(ij) so that W_(ij)=u_(ij) ^(T)

_(ij); and determining the output vector y from y=W·x, where W is a matrix composed of all submatrices W_(ij) for i=(1, . . . , m/s) and j=(1, . . . , n/t).
 16. The system of claim 15, wherein determining the output vector y from y=W·x comprises: computing y_(i)=Σ_(j=1) ^(n/t)(W_(ij)x_(j)); and determining the output vector y as y=[y₁, y₂, y₃, . . . , ym_(/s)].
 17. The system of claim 15, wherein determining the output vector y from y=W·x comprises: appending submatrices W_(ij) to obtain matrix W; and computing y=W·x.
 18. The system of claim 15, wherein the neural network is a feedforward neural network.
 19. The system of claim 15, wherein the neural network is a deep neural network. 